Wang, H. (CSE) – Accelerating RTL Simulation with Specialized Graph Partitioners
Register transfer level (RTL) simulation is an invaluable tool for developing, debugging, verifying, and validating hardware designs. However, the performance of RTL simulation has long been a limiting factor in industry. Despite the inherent parallelism of hardware, current RTL simulators have not achieved practical performance gains due to fundamental challenges in communication, synchronization, memory bandwidth, […]