Garg, S. (CSE) – MAPPING ANNOTATIONS FROM NETLIST TO SOURCE CODE
Hardware design flows have become increasingly complex as modern chips integrate billions
of transistors and rely on aggressive synthesis optimizations to meet performance,
area, and power targets. While these transformations improve circuit efficiency, they
also erase the correspondence between gate-level netlists and their originating HDL
source lines. The loss of traceability makes post-synthesis debugging, timing backannotation,
and root-cause analysis extremely difficult. Existing solutions depend on
tool-specific metadata or preserved signal names, which are often lost after flattening,
retiming, or logic restructuring.
To address this long-standing problem, this thesis presents SynAlign, a structural
alignment framework that restores the mapping between optimized netlists and
source code without relying on synthesis metadata. SynAlign treats both the reference
RTL and synthesized designs as graphs and iteratively aligns them using shared
structural cues—such as sequential boundaries, fan-in/fan-out relationships, and partial
naming patterns. The algorithm employs anchor-based seeding, multi-stage neighborhood
matching, and a lightweight scoring function to propagate correspondences
efficiently across large designs.
Extensive evaluation demonstrates that SynAlign achieves over 90% line-level
alignment accuracy across diverse designs, maintaining robustness even when 60% of
signal names are obfuscated or removed. The framework scales linearly with design size,
completing alignment on multi-million-node circuits within minutes. Controlled tests
confirmed structural stability under synthetic noise, while production-level validation
on real processor and accelerator modules verified industrial applicability.
By recovering structural visibility lost during synthesis, SynAlign bridges a
critical gap between front-end design intent and post-synthesis implementation. Its explainable
alignment enables faster debug cycles, more accurate timing correlation, and
provides a foundation for next-generation EDA tools that integrate traceability, optimization
transparency, and source-level introspection into the hardware development
process.
Host: Sakshi Garg, Ph.D. Candidate, Computer Science and Engineering
Advisor: Jose Renau
Zoom- https://ucsc.zoom.us/j/96207792766?pwd=bjBfusfaucoqMGZNgayum2te4tsLc5.1
Passcode- 669162
