Sheaves, T. (CSE) – Timing Side-Channels in Commercial ReRAM: Toward ReRAM Pentimenti

Recently, a class of non-invasive hardware side-channel attacks has been discovered in field-programmable gate arrays (FPGAs). These attacks extract remnants of prior users’ activity that persist as transistor defect states within reconfigurable routing resources. These remnants are known as FPGA Pentimenti. Resistive random-access memory (ReRAM) is a compelling candidate for pentimenti-like attacks beyond FPGAs. However, unlike FPGAs, where sophisticated on-chip sensors capable of detecting pentimenti have been well-studied, non-invasive pentimenti recovery in commercial ReRAM must rely on measurements of observable write latency. These measurements are dominated by data-dependent structural biases that obscure any underlying defect-dynamics signal. In this dissertation, we demonstrate that the structural and stochastic components of commercial ReRAM write latency can be decoupled and recovered through non-invasive timing analysis alone. Our results provide the reverse engineering and measurement infrastructure for future study of ReRAM pentimenti by isolating the component of programming latency sensitive to defect dynamics.

Event Host: Tyler Sheaves, Ph.D. Candidate, Computer Science & Engineering 

Advisor: Dustin Richmond 

Zoom: https://ucsc.zoom.us/j/92729427179?pwd=BpYLqft18YdOU0mDdQWs8erID2VcHi.1

Passcode: 939530